Field of the Invention
The present invention relates generally to a method, system, and apparatus for a semiconductor using fully aligned via (FAV) reactive ion etching (RIE), and more particularly relates to a method, system, and apparatus to improve FAV RIE process margin and Electromigration resistance.
Description of the Related Art
The fabrication of Very-Large Scale Integrated (VLSI) requires an interconnect structure including metallic wiring that connects individual devices in a single semiconductor chip. With the chip being massively reduced in size over the years, the interconnect structure has also been reduced accordingly. The via levels are one of the most challenging to print. Additionally, there are overlay errors that result from misalignment during the lithography. The overlay errors may lead to reliability issues.
A failure for interconnects that may be dependent on overlay error of lithographic patterns, are electromigration (EM) and time-dependent dielectric breakdown (TDDB). Overlay errors in the related art result in reduced spacing between the via and the metal level below, and therefore increase the dielectric field. There is a need to provide a technique of reducing the spacing variation.
There is a need to providing a technique of forming a fully aligned via that is more efficient and avoids affecting yield and reliability issues such that there is an improvement in process margin and Electromigration resistance.